The systems on chip (SoC) are the most complex integrated circuits designed by the top class engineers with the expertise on mixed analog and digital signal design, knowing the technology of embedded computing and a deep understanding of the different sensors integrated on chip and familiar with the additional processing techniques like MEMS fabrication, process modifications etc.
In the talk a brief history of the mixed signal circuit design theory development is presented in terms of addressing the problems when joining the digital design with the sensitive analog design.
It is a complex task to join two different design techniques to a successful mixed signal ASIC. Few examples of the mixed signal designs are presented, demonstrating the top down system level design approach. The possibility to include the embedded microprocessor is opening the door to systems on chip with unprecedented capabilities.
The inclusion of integrated sensors enable such systems on chip to play an important role in our life in the area of personal health devices, helping to perform our daily routines more efficiently and improve our well-being and much more.
Professor Janez Trontelj is a Head of the Laboratory for Microelectronics at the Faculty of Electrical Engineering, University of Ljubljana. He graduated in 1965 at the Faculty of Electrical Engineering in University of Ljubljana and received his Master's and PhD degree in 1969 and 1971, subsequently. He is a principal author of the first scientific book on mixed circuit design “Analog Digital ASIC Design” published by McGraw Hill in 1989. He authored or co-authored 26 granted patents, 13 of them being international. The major results of his research work are the development of telecommunication and automotive microcircuits, as well as magnetic and mechanical microsystems, which are being produced in millions yearly.
He is internationally recognized as an expert on magnetic sensor technology, Terahertz sensors and systems. He designed more than a dozen ASICs with integrated smart sensor systems used for different applications. He is the recipient of many national awards and is a member of Slovenian Academy of Engineering. He has held several invited talks at imminent conferences.
Digital transformation is having a significant impact in our society. Embedded computing is becoming a key technology that is further evolving with the recent addition of embedded Artificial Intelligence capabilities. These products integrate more and more technologies that allow for advanced interactions with their environment, with ever more increased autonomy. Examples go from autonomous cars, connected planes, intelligent grids in the energy domain or Industry 4.0. These important evolutions share a common concept: mastering connected and intelligent systems called CyberPhysical Systems. This talk will present some important trends for this market and the associated technological challenges gathered during a study performed with the financial support of the French national directorate for Industry (DGE) and Embedded France, a not-for-profit association which unites key French players in software and embedded systems, as well as some technology trends identified during the on-going European Excel project CPS4EU.
Engineer from TelecomParis school in 1983, Cédric Demeure obtained his Master degree from the University of Rhode-Island (USA) in 1984, and his PhD in Signal Processing at the University of Colorado in 1989 after a year studying SAR radars in Thomson-CSF. In 1990, he joined the Communications division of Thomson-CSF to work on digital radios and modems. In 1992, he became responsible of the advanced study laboratory in Antenna Processing for direction finding and spectrum surveillance. In 1996, he became manager of the Signal and Image Processing Department. From 2004 till 2013, he was the director of the Digital Embedded Systems Unit, dealing with all advanced studies and product development (both SW and HW) for wireless communications products. Since October 2013, Cédric Demeure is VP R&T for Thales in France and thus the director of the corporate Research and Technology entity in Palaiseau. Located on the Ecole Polytechnique campus, this research center mainly performs studies in materials, in physics and electronic components, in optics and also in information science and technologies (both in computing and algorithms). Since 2016 he is the president of the Embedded France, a non-profit association joining together French representatives of embedded software and system actors, and is a member of the national Strategic Council for Electronics.
The Internet of Things (IoT) is an extremely diverse market and can be defined as anything from sensors to cars. It is estimated that over 30 billion IoT devices will ship by 2020. The ability to sense countless amount of information that communicates between edge devices to the cloud is driving innovation into IoT applications, from wearable devices (for health, fitness or infotainment) to in machine-to-machine applications in smart appliances, smart cities or commerce. It has become crucial for today’s IoT chips to use a range of new solutions during the design stage to ensure the robustness of manufacturing quality, field reliability, safety and security. DFT designers need to use new solutions to enable power reductions during test, concurrent checking, isolated debug and diagnosis, safety monitoring, secure access, calibration, and uniform fabric. Moreover, the per unit IoT price remains a key factor in high volume production. Thus, minimizing the robustness cost while meeting the above technical issues is one of the major challenges of the IoT industry. This presentation, besides discussing the key trends and challenges of IoT, will cover solutions to handle the wide range of potential robustness challenges during all periods of the IoT creation and lifecycle from design, post silicon bring-up, volume production, to in-system operation.
Dr. Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, has been the Vice President of IEEE Computer Society for Conferences, Technical Activities, Membership and Geographic Activities, and the General Chair of the 50th Design Automation Conference (DAC); the 50th International Test Conference and several other symposia and workshops.
Dr. Zorian holds 40 US patents, has authored five books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science.
He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.
In 2018, the European Commission announced the creation of the European Processor Initiative (EPI), a European consortium to co-design, develop and bring to the market a European low-power microprocessor. EPI started at the end of 2018 and will develop the first European High Performance Computing (HPC) System on Chip (SoC), and multiple domain-specific accelerators. Both elements, SoCs and accelerators, will be implemented and validated in a prototype system that will become the basis for a full Exascale machine based on European technology.
In this talk, we will briefly introduce the EPI objectives and will focus on the role we play in designing the European HPC SoC and accelerators. In the past years, BSC has promoted incorporating Arm-based processors in the HPC market in multiple European projects (Mont-Blanc, EuroEXA, Exanode, etc.), while it has recently started developing its own accelerator based on the RISC-V open ISA. Lessons learned from these past experiences will allow BSC to contribute to the success of EPI and pave the way towards open hardware designs across Europe.
Miquel Moreto is a Ramon-y-Cajal Researcher at UPC and an associate researcher at the Barcelona Supercomputing Center (BSC). Prior to joining UPC, he was a Fulbright Postdoctoral Research Fellowship Holder at the International Computer Science Institute (ICSI), affiliated with UC Berkeley, from 2012 to 2013. He received the B.Sc., M.Sc., and Ph.D. degrees from UPC. His research interests include high performance computer architectures and hardware-software co-design for future massively parallel systems.